The invention relates to analyzing interconnect structures and more specifically to analyzing such structures using modeling techniques.
Interconnect structures (also termed “interconnects”) are used to connect circuitry and may be located either on or off of a semiconductor device or chip. The accurate analysis of such structures is of great importance to high speed chip design since the performance of interconnects has impact on signal delay, signal decay, cross talk, and power delivery. Such analysis becomes more important as the clock frequency of microprocessors increases, heading to the 20 gigahertz (GHz) level in the 0.13 micron (μm) processing generation and beyond. However, the computational complexity of interconnects especially on-chip interconnects resulting from high conductor loss, strong skin effect, non-uniform dielectric, orthogonal layers, and large aspect ratio prevents an efficient and rigorous analysis of large-scale three-dimensional (3D) interconnects.
Two modeling methodologies for 3D on-chip interconnects have been adopted. One manner of analyzing interconnect structures, particularly 3-dimensional (3D) structures, is by extracting resistance (R), inductance (L), and capacitance (C) using computer aided design (CAD) tools and inputting the results into a circuit simulator. However, this approach is based on low frequency approximation, the validity of which is questionable at high frequencies. Another manner of analyzing an interconnect is to partition it into subcircuits and input the parts into a full-wave solver and cascade each subcircuit to extract the overall circuit behavior. However, this approach cannot model electromagnetic coupling correctly. To correctly do so, the entire 3D structure must be simulated instead of partitioning it first. However, a 3D interconnect structure can involve billions of unknowns, which no current computational resources can tolerate.
Thus a need exists to accurate and efficiently analyze interconnect structures, such as large scale 3D structures.